My invention relates to instruments, known to the specialists as logic analyzers, for visual presentation of logic signals, and more specifically to a composite logic analyzer capable of simultaneously (or independently) displaying two sets of logic signals in different, time-related formats. My invention will be disclosed herein as adapted for a combined logic state and timing analyzer, exhibiting data in the state-table and/or timing-diagram format, but with no unnecessary limitations thereto being intended.
Logic analyzers have been classified as either timing analyzers or state analyzers. The logic timing analyzer might be described as a multichannel digital-storage oscilloscope, normally with four to 16 input terminals for the reception of, for example, control signals from computer logic circuitry. Usually, the timing analyzer has an internal clock capable of generating a plurality of periodic signals at high recurrence rates. Any selected one of the clock signals is used for sampling the incoming control signals, and the captured samples are stored in random-access semiconductor memories as logic signals. Also included is a display circuit which reads out the memories repetitively and recreates the input signals as two-level waveforms, for display on a cathode-ray tube (CRT) in the timing diagram format.
From the displayed timing diagram the viewer can evaluate the timing relationships between the logic level changes, the presence or absence of pulses, the pulse durations, and other events of interest. Further the timing analyzer is normally constructed to detect glitches or spurious narrow pulses appearing between the clock pulses.
The logic state analyzer, on the other hand, may have 16 to 32 input terminals for connection, for example, to the data or address bus of the computer's central processing unit (CPU). The state analyzer is externally clocked, inputting the reference clock signal of the data or address bus signals. For this reason the sampling and storage of the data in the state analyzer proceed at a lower rate than in the timing analyzer. The state analyzer displays the captured bus data in the form of a state table, which contains successive sets of numerals or alphanumerics representing the data in binary, octal, or hexadecimal notation for the ease of interpretation. The state table enables the observer to ascertain the varying states of the bus.
Although intended for different purposes as above, the timing analyzer and the state analyzer are alike in basic configuration. The logic analyzer has been suggested, therefore, which can be switched between state analysis and timing analysis mode. This known instrument permits data display only in the state table or timing diagram format.
A more advanced composite logic analyzer has been developed wherein a complete state analyzer and a complete timing analyzer are unitized, only with a trigger generator shared by both analyzer sections, for simultaneous (or selective) display of a timing diagram and a state table on a common CRT screen. This advanced logic state and timing analyzer has its own drawback, however. The drawback arises from the fact that its state analyzer section is externally clocked, whereas the timing analyzer section is internally clocked. The repetition frequencies of the external and internal clock signals differ. Thus, except for the common moment of triggering, no time relationship can be ascertained between the data captured in the state analyzer section and displayed in the state table format and the data captured in the timing analyzer section and displayed on the same screen in the timing diagram format.